The present invention relates to a peripheral device selection interface for a digital microprocessor, and more specifically to a port select unit for a serial-bit, programmable microinstruction processor. The subject invention, furthermore, is designed for a particular type of processor unit as embodied in the teachings of Faber in patent application Ser. No. 307,863, filed Nov. 20, 1972 now U.S. Pat. No. 3,878,514 and assigned to the same assignee of the present application. The programmable unit disclosed therein is a serial-bit with byte transfer processor employing soft machine architecture through microprogramming. An instruction set, at the microprogram level, is provided for controlling the specific circuitry of the processor in executing basic computer operations. Essentially, the specific circuitry represents minimally committed logic or hardware which becomes committed to a specific task by control signals originating in the instruction set. Logic, control and addressing functions are performed by circuitry which includes only those gates, registers, drivers and related logic, which are necessary to implement the basic operations.
Such a processing unit may be comprised of five functional parts: (1) a logic unit which performs shifting, arithmetic and logic functions; (2) a microprogram memory which stores both literals and control words; (3) a memory control unit which provides the registers microprogram memory addressing; (4) a control unit which provides timing and conditional control, successor determination and instruction decoding; and (5) and external interface.
In the microprocessor, cited above, a microprogram memory (MPM) is addressed by a memory program count register (MPCR). Feeding this (MPCR) register is an alternate memory program count register (AMPCR). The AMPCR receives instructions from microprogram memory as well as from other registers within the processor.
Microprocessors of the Faber type are being used in larger and more complicated processing tasks than for which they were originally designed. While this processor's logic units and control units are sophisticated enough to handle the enlarged processing tasks, the micromemory capacity as designed into the basic apparatus is not large enough. This shortcoming of limited memory capacitor exists in most microprocessors in the class of Faber size processors. The compactness of the basic processor as implemented in a single MOS chip or in a single TTL-printed circuit card unit did not, with yesterday's technology, permit extensive micromemory capacity. In an installation where more memory capacity is needed this capacity must be peripheral to the basic processor and be addressed through the processor interface.
Moreover, in a typical processor application, a variety of peripheral devices, such as process sensors, process controllers, tape reader/writers, transmission terminals, etc., will be connected to the basic microprocessor. The basic processor must access each peripheral in order to communicate with that peripheral.
An interface concept which has been introduced in conjunction with a parallel operation, microinstruction processor system, capable of multiple processing, is port selection. This concept enables communication interlocking between each of the processor and the peripheral devices and has involved a definition of all peripherals as being on an equal plane, regardless of function, and as being located at a specific address. Information buses to each peripheral device can thusly be considered as portals or ports to that device through which that device may be accessed. A port select from the processor will control the opening of a specific port.
The port selection for a parallel processor multiprocessing system, however, involved a complex interlocking signal scheme dependent upon various status signals and interrupt signals to monitor each data port. The selection unit was dependent upon locked and unlocked status modes, selected and unselected status modes and data interrupt signals. A priority selection logic unit was employed to monitor signal operation. The complexity of such a port select unit resulted in relatively slow operation of peripheral selection and consequently a slower processing speed for the entire system. It would be desirable, therefore, to have a port selection unit for a serial-bit microinstruction processor which is capable of higher operating speeds.
An objective of this invention is to provide a simplified port selection apparatus and method for interfacing a serial-bit microinstruction processor to a plurality of peripheral devices in a single processor system.
Another objective of this invention is to provide an exclusive port selection apparatus wherein only one peripheral at a time communicates with the processor.
A further objective of this invention is to provide a port selection unit which is easily expanded with minimal impact, if any, upon the existing circuit design.